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DRIVER SWITCHING CHARACTERISTICS RECEIVER ELECTRICAL CHARACTERISTICS SN65HVD1040A-Q1 www.ti.com....................................................................................................................................................................................................... SLLS889 – JUNE 2008 over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high level output STB at 0 V, See Figure 4 25 65 120 ns tPHL Propagation delay time, high-to-low level output STB at 0 V, See Figure 4 25 45 120 ns tr Differential output signal rise time STB at 0 V, See Figure 4 25 ns tf Differential output signal fall time STB at 0 V, See Figure 4 45 ns ten Enable time from standby mode to dominant See Figure 7 10 µs t(dom) Dominant time out(2) 300 450 700 µs (1) All typical values are at 25°C with a 5-V supply. (2) The TXD dominant time out (t(dom)) disables the driver of the transceiver once the TXD has been dominant longer than t(dom), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(dom) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t(dom) = 11 bits / 300 µs = 37 kbps over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Positive-going input threshold voltage, VIT+ STB at 0 V, See Table 1 800 900 mV high-speed mode Negative-going input threshold voltage, VIT– STB at 0 V, See Table 1 500 650 mV high-speed mode Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV VIT Input threshold voltage, standby mode STB at VCC 500 1150 mV VOH High-level output voltage 4 4.6 V VOL Low-level output voltage 0.2 0.4 V CANH = CANL = 5 V, II(off) Power-off bus input current 3 µA VCC at 0 V, TXD at 0 V IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA TXD at 3 V, CI Input capacitance to ground (CANH or CANL) 13 pF VI = 0.4 sin (4E6πt) + 2.5 V CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 6 pF RID Differential input resistance TXD at 3 V, STB at 0 V 30 80 k Ω RIN Input resistance (CANH or CANL) TXD at 3 V, STB at 0 V 15 30 40 k Ω Input resistance matching RI(m) V(CANH) = V(CANL) –3 0 3 % [1 – (RIN (CANH) / RIN (CANL))] × 100% (1) All typical values are at 25°C with a 5-V supply. Copyright © 2008, Texas Instruments Incorporated 5 |
