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74AUP1G332GW Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G332GW Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74AUP1G332_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 29 February 2008 3 of 16 NXP Semiconductors 74AUP1G332 Low-power 3-input OR gate 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP1G332 AC GND BY 001aad930 1 2 3 6 VCC 5 4 74AUP1G332 GND 001aad931 A B VCC C Y Transparent top view 2 3 1 5 4 6 74AUP1G332 GND 001aad932 A B VCC C Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description A 1 data input A GND 2 ground (0 V) B 3 data input B Y 4 data output Y VCC 5 supply voltage C 6 data input C Table 4. Function table[1] Input Output A B C Y H XXH XH XH XXH H LLLL |
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