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74AUP1G80GM Datasheet(PDF) 11 Page - NXP Semiconductors |
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74AUP1G80GM Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 18 page 74AUP1G80_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 20 October 2006 11 of 18 NXP Semiconductors 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger 12. Waveforms Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The clock input (CP) to output (Q) propagation delays mna652 CP input Q output tPLH tPHL VM VM VOH VI GND D input VI GND VOL VM VM Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. The clock input (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up and hold times and the maximum input clock frequency mna653 th tsu(L) th tPLH tW tPHL tsu(H) 1/fmax VM VM VM VI GND VI GND CP input D input VOH VOL Q output Table 9. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × V CC 0.5 × V CC VCC ≤ 3.0 ns |
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