74AUP1G09GW datasheet(9/15 Pages) NXP

Part #	74AUP1G09GW

Description	Low-power 2-input AND gate with open-drain

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Manufacturer	NXP [NXP Semiconductors]

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9 / 15 page

74AUP1G09_1

Product data sheet

Rev. 01 — 15 January 2009

9 of 15

NXP Semiconductors

74AUP1G09

Low-power 2-input AND gate with open-drain

[1]

For measuring enable and disable times RL = 5 kΩ.

For measuring propagation delays, set-up and hold times, and pulse width, RL = 1 MΩ.

Test data is given in Table 10.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 8.

Test circuit for measuring switching times

001aac521

DUT

RT

VI

VO

VEXT

VCC

RL

5 k

Ω

CL

G

Table 10.

Test data

Supply voltage

Load

VEXT

VCC

CL

RL[1]

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

5 k

Ω or 1 MΩ open

GND

2VCC

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