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74ABT16821ADL Datasheet(PDF) 9 Page - NXP Semiconductors |
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74ABT16821ADL Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74ABT16821A_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 16 March 2010 9 of 16 NXP Semiconductors 74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state 11. Waveforms VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency 001aae858 tPHL tPLH tWH tWL 1 / fmax VM VM VM VM VM nCP nQx 0 V VOH VOL VI VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. 3-state output enable time to HIGH-level and output disable time from HIGH- level 001aal294 tPLZ tPHZ outputs disabled outputs enabled VOH − 0.3 V VOL + 0.3 V outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH 3.5 V VM GND GND tPZL tPZH VM VM |
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