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X28HC64KM-12 Datasheet(PDF) 5 Page - Xicor Inc. |
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X28HC64KM-12 Datasheet(HTML) 5 Page - Xicor Inc. |
5 / 24 page X28HC64 5 THE TOGGLE BIT I/O 6 Figure 4. Toggle Bit Bus Sequence Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC64 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. 3857 FHD F15 LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n READY COMPARE OK? NO YES LAST WRITE 3857 FHD F14 CE OE WE I/O6 X28HC64 READY VOH VOL LAST WRITE HIGH Z * Beginning and ending state of I/O6 will vary. * * |
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