 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DAC3283IRGZR Datasheet(PDF) 8 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
DAC3283IRGZR Datasheet(HTML) 8 Page - Texas Instruments |
|
|
8 / 50 page  DAC3283 SLAS693A – MARCH 2010 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INTERFACE:D[7:0]P/N, DATACLKP/N, FRAMEP/N (1) Byte-wide DDR format fDATA Input data rate 312.5 MSPS DATACLK frequency = 625 MHz fBUS Byte-wide LVDS data transfer rate 1250 MSPS VA,B+ Logic high differential input voltage threshold 150 400 mV VA,B– Logic low differential input voltage threshold –150 –400 mV VCOM Input common mode 0.9 1.2 1.5 V ZT Internal termination 85 110 135 Ω CL LVDS Input capacitance 2 pF TIMING LVDS INPUTS: DATACLKP/N DOUBLE EDGE LATCHING – See Figure 40 Setup time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge of ts(DATA) –25 ps to either edge of DATACLKP/N DATACLKP/N only Hold time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge of th(DATA) 375 ps after either edge of DATACLKP/N DATACLKP/N only t(FRAME) FRAMEP/N pulse width fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns Maximum offset between DATACLKP/N and FIFO bypass mode only fDACCLK is 1/2fDACCLK t_align ns DACCLKP/N rising edges DACCLK frequency in MHz –0.55 CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% Differential voltage(2) 0.4 1.0 V DACCLKP/N Input Frequency 800 MHz OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK / (n × 8 × Interp) where n is fDACCLK / (8 fOSTR Frequency any positive integer fDACCLK is DACCLK x interp) frequency in MHz Duty cycle 40% 60% Differential voltage 0.4 1.0 V TIMING OSTRP/N INPUT: DACCLKP/N RISING EDGE LATCHING Setup time, OSTRP/N valid to rising edge of ts(OSTR) 200 ps DACCLKP/N Hold time, OSTRP/N valid after rising edge th(OSTR) 200 ps of DACCLKP/N CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE VIH High-level input voltage 1.25 V VIL Low-level input voltage 0.54 V IIH High-level input current –40 40 mA IIL Low-level input current –40 40 mA CI CMOS input capacitance 2 pF DIGVDD18 Iload = –100 mA V –0.2 VOH ALARM_SDO, SDIO 0.8 x Iload = –2mA V DIGVDD18 Iload = 100 mA 0.2 V VOL ALARM_SDO, SDIO Iload = 2 mA 0.5 V SERIAL PORT TIMING – See Figure 32 and Figure 33 ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns Setup time, SDIO valid to rising edge of ts(SDIO) 10 ns SCLK th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns Register CONFIG5 read (temperature 1 ms sensor read) t(SCLK) Period of SCLK All other registers 100 ns (1) See LVDS INPUTS section for terminology. (2) Driving the clock input with a differential voltage lower than 1V will result in degraded performance. 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DAC3283 |
Similar Part No. - DAC3283IRGZR |
|
Similar Description - DAC3283IRGZR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
