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ADAU1401AWBSTZ-RL Datasheet(PDF) 10 Page - Analog Devices |
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ADAU1401AWBSTZ-RL Datasheet(HTML) 10 Page - Analog Devices |
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10 / 52 page  ADAU1401A Rev. 0 | Page 10 of 10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 AVDD PLL_LF PVDD PGND MCLKI OSCO RSVD MP2/SDATA_IN2/AUX_ADC1 MP3/SDATA_IN3/AUX_ADC2 MP8/SDATA_OUT2/AUX_ADC3 MP9/SDATA_OUT3/AUX_ADC0 DGND AGND ADC1 ADC_RES ADC0 RESET SELFBOOT ADDR0 MP4/INPUT_LRCLK MP5/INPUT_BCLK MP1/SDATA_IN1 MP0/SDATA_IN0 DGND 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 ADAU1401A TOP VIEW (Not to Scale) PIN 1 INDICATOR Figure 7. 48-Lead LQFP Pin Configuration Table 11. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1, 37, 42 AGND PWR Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. AGND should be decoupled to an AVDD pin with a 100 nF capacitor. 2 ADC1 A_IN Analog Audio Input 1. Full-scale 100 μA rms input. The current input allows the input voltage level to be scaled with an external resistor. An 18 kΩ resistor results in a 2 V rms full-scale input. See the Audio ADCs section for details. 3 ADC_RES A_IN ADC Reference Current. The full-scale current of the ADCs can be set with an external 18 kΩ resistor connected between this pin and ground. See the Audio ADCs section for details. 4 ADC0 A_IN Analog Audio Input 0. Full-scale 100 μA rms input. The current input allows the input voltage level to be scaled with an external resistor. An 18 kΩ resistor results in a 2 V rms full-scale input. 5 RESET D_IN Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1401A exits reset on a low-to-high edge. For more information about initialization, see the Power-Up Sequence section for details. 6 SELFBOOT D_IN Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting this pin high initiates a self-boot operation when the ADAU1401A is brought out of a reset. This pin can be tied directly to the control voltage or pulled up/down with a resistor. See the Self-Boot section. 7 ADDR0 D_IN I2C and SPI Address 0. In combination with ADDR1, this pin allows up to four ADAU1401A devices to be used on the same I2C bus or up to two ICs to be used with a common SPI CLATCH signal. See the I2C Port section for details. 8 MP4/INPUT_LRCLK D_IO Multipurpose GPIO/Serial Input Port LRCLK. See the Multipurpose Pins section for more details. 9 MP5/INPUT_BCLK D_IO Multipurpose GPIO/Serial Input Port BCLK. See the Multipurpose Pins section for more details. 10 MP1/SDATA_IN1 D_IO Multipurpose GPIO/Serial Input Port Data 1. See the Multipurpose Pins section for more details. 11 MP0/SDATA_IN0 D_IO Multipurpose GPIO/Serial Input Port Data 0. See the Multipurpose Pins section for more details. 12, 25 DGND PWR Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. DGND should be decoupled to a DVDD pin with a 100 nF capacitor. 13, 24 DVDD PWR 1.8 V Digital Supply. The input for this pin can be supplied either externally or generated from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be decoupled to DGND with a 100 nF capacitor. |
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