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ADAU1401AWBSTZ Datasheet(PDF) 11 Page - Analog Devices |
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ADAU1401AWBSTZ Datasheet(HTML) 11 Page - Analog Devices |
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11 / 52 page  ADAU1401A Rev. 0 | Page 11 of 11 Pin No. Mnemonic Type1 Description 14 MP7/SDATA_OUT1 D_IO Multipurpose GPIO/Serial Output Port Data 1. See the Multipurpose Pins section for more details. 15 MP6/SDATA_OUT0/ TDM_IN D_IO Multipurpose GPIO/Serial Output Port Data 0/TDM Data Input. See the Multipurpose Pins section for more details. 16 MP10/OUTPUT_LRCLK D_IO Multipurpose GPIO/Serial Output Port LRCLK. See the Multipurpose Pins section for more details. 17 VDRIVE A_OUT Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is driven from VDRIVE. See the Voltage Regulator section for details. 18 IOVDD PWR Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage that should be seen on the digital input pins. This pin is also the supply for the digital output signals on the control port and MPx pins. IOVDD should always be set to 3.3 V. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. 19 MP11 D_IO Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins section for more details. 20 ADDR1/CDATA/WB D_IN I2C Address 1/SPI Data Input/EEPROM Writeback Trigger. ADDR1 in combination with ADDR0 sets the I2C address of the IC so that four ADAU1401A devices can be used on the same I2C bus (see the I2C Port section for details). For more information about the CDATA function of this pin, see the SPI Port section. A rising (default) or falling (if set by EEPROM messages) edge on the WB pin triggers a writeback of the interface registers to the external EEPROM. This function can be used to save parameter data on power-down (see the Self-Boot section for details). 21 CLATCH/WP D_IO SPI Latch Signal/Self-Boot EEPROM Write Protect. CLATCH must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction can take a different number of cycles on the CCLK pin to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction (see the SPI Port section for details). The WP pin is an open-collector output when the device is in self-boot mode. The ADAU1401A pulls WP low to enable writes to an external EEPROM. This pin should be pulled high to 3.3 V (see the Self-Boot section for details). 22 SDA/COUT D_IO I2C Data/SPI Data Output. SDA is a bidirectional open collector. The line connected to SDA should have a 2.2 kΩ pull-up resistor (see the I2C Port section for details). COUT is used for reading back registers and memory locations. It is three-stated when an SPI read is not active (see the SPI Port section for details). 23 SCL/CCLK D_IO I2C Clock/SPI Clock. SCL is always an open-collector input when in I2C control mode. In self-boot mode, SCL is an open-collector output (I2C master). The line connected to SCL should have a 2.2 kΩ pull-up resistor (see the I2C Port section for details). CCLK can either run continuously or be gated off between SPI transactions (see the SPI Port section for details). 26 MP9/SDATA_OUT3/ AUX_ADC0 D_IO/A_IO Multipurpose GPIO/Serial Output Port Data 3/Auxiliary ADC Input 0. See the Multipurpose Pins section for more details. 27 MP8/SDATA_OUT2/ AUX_ADC3 D_IO/A_IO Multipurpose GPIO/Serial Output Port Data 2/Auxiliary ADC Input 3. See the Multipurpose Pins section for more details. 28 MP3/SDATA_IN3/ AUX_ADC2 D_IO/A_IO Multipurpose GPIO/Serial Input Port Data 3/Auxiliary ADC Input 2. See the Multipurpose Pins section for more details. 29 MP2/SDATA_IN2/ AUX_ADC1 D_IO/A_IO Multipurpose GPIO/Serial Input Port Data 2/Auxiliary ADC Input 1. See the Multipurpose Pins section for more details. 30 RSVD Reserved. Tie this pin to ground, either directly or through a pull-down resistor. 31 OSCO D_OUT Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be connected between this pin and the crystal. This output should not be used to directly drive a clock to another IC. If the crystal oscillator is not used, this pin can be left unconnected. See the Using the Oscillator section for details. 32 MCLKI D_IN Master Clock Input. This pin can either be connected to a 3.3 V clock signal or be the input from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for details. 33 PGND PWR PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor. 34 PVDD PWR 3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This pin should be decoupled to PGND with a 100 nF capacitor. 35 PLL_LF A_OUT PLL Loop Filter Connection. Two capacitors and a resistor must be connected to this pin, as shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details. 36, 48 AVDD PWR 3.3 V Analog Supply. This pin should be decoupled to AGND with a 100 nF capacitor. |
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