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XM28C020P-20 Datasheet(PDF) 6 Page - Xicor Inc. |
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XM28C020P-20 Datasheet(HTML) 6 Page - Xicor Inc. |
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6 / 16 page  XM28C020 6 memory ICs and decoder should be considered memory board components and SDP can be implemented at the component level as described in the next section. SOFTWARE COMMAND SEQUENCE A16 and A17 are used by the decoder to select one of the four LCCs. Therefore, only one of the four memory devices can be accessed at one time. In order to protect the entire module, the command sequence must be issued separately to each device. Enabling the software data protection mode requires the host system to issue a series of three write operations: each write operation must conform to the data and address sequence illustrated in Figures 6 and 7. Because this involves writing to a nonvolatile bit, the device will become protected after tWC has elapsed. After this point in time devices will inhibit inadvertent write operations. Once in the protected mode, authorized writes may be performed by issuing the same command sequence that enables SDP, immediately followed by the address/data combination desired. The command sequence opens the page write window enabling the host to write from one to 128 bytes of data. Once the data has been written, the device will automatically be returned to the protected state. In order to facilitate testing of the devices the SDP mode can be deactivated. This is accomplished by issuing a series of six write operations: each write operation must conform to the data and address sequence illustrated in Figures 8 and 9. This is a nonvolatile operation, and the host will have to wait a minimum tWC before attempting to write new data. HARDWARE DATA PROTECTION The XM28C020 provides three hardware features that protect nonvolatile data from inadvertent writes. • Noise Protection—A WE pulse less than 10ns will not initiate a write cycle. • Default VCC Sense—All functions are inhibited when VCC is ≤ 3V. • Write Inhibit—Holding OE LOW will prevent an inad- vertent write cycle during power-up and power-down. SOFTWARE DATA PROTECTION The XM28C020 does provide the Software Data Protec- tion (SDP) feature. The module is shipped from Xicor with the Software Data Protection NOT ENABLED; that is, the module will be in the standard operating mode. In this mode, data should be protected during power-up/-down operations through the use of external circuits. The host system will then have open read and write access of the module once VCC is stable. The module can be automatically protected during power- up/-down without the need for external circuits by em- ploying the SDP feature. The internal SDP circuit is enabled after the first write operation utilizing the SDP command sequence. When this feature is employed, it will be easiest to incorporate in the system software if the module is viewed as a subsystem composed of four discrete memory devices with an address decoder (see Func- tional Diagram). In this manner, system memory map- ping will extend onto the module. That is, the discrete |
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