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X25F016VI Datasheet(PDF) 3 Page - Xicor Inc. |
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X25F016VI Datasheet(HTML) 3 Page - Xicor Inc. |
3 / 16 page X25F064/032/016/008 3 formatted as follows: PPEN, BL0, and BL1 are set by the PRSR instruction. PEL and PIP are “read-only” and automatically set by other operations. The Programming-In-Process (PIP) bit indicates whether the X25F064/032/016/008 device is busy with a program operation. When set to a “1” programming is in progress, when set to a “0” no programming is in progress. During programming, all other bits are set to “1”. The Program Enable Latch (PEL) bit indicates the status of the program enable latch. When set to a “1” the latch is set; when set to a “0” the latch is reset. The Block Lock (BL0 and BL1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25F064/032/016/008 device array is divided into four equal segments. One, two, or all four of the seg- ments may be locked. That is, the user may read the segments, but will be unable to alter (program) data within the selected segments. The partitioning is con- trolled as illustrated below. Status Register Bits Array Addresses BL1 BL0 Locked 0 0 None 0 1 upper fourth 1 0 upper half 1 1 All 6685 PGM T03.1 Program-Protect Enable The Program-Protect-Enable bit (PPEN) in the X25F064/032/016/008 status register acts as an enable bit for the PP pin. PRINCIPLES OF OPERATION The X25F064/032/016/008 family are SerialFlash Memory designed to interface directly with the synchro- nous serial peripheral interface (SPI) of many popular microcontroller families. The X25F064/032/016/008 family contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and PP inputs must be HIGH during the entire operation. The PP input is “Don’t Care” if PPEN is set “0”. Table 1 contains a list of the instructions and their operation codes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25F064/ 032/016/008 into a “PAUSE” condition. After releasing HOLD, the X25F064/032/016/008 device will resume operation from the point when HOLD was first asserted. Program Enable Latch The X25F064/032/016/008 device contains a program enable latch. This latch must be SET before a program operation will be completed internally. The PREN instruction will set the latch and the PRDI instruction will reset the latch. This latch is automatically reset on power-up and after the completion of a sector program or status register write cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a program cycle. The status register is 7 654 3 2 1 0 PPEN X X X BL1 BL0 PEL PIP 6685 PGM T02.2 Table 1. Instruction Set Instruction Name Instruction Format* Operation PREN 0000 0110 Set the Program Enable Latch (Enable Program Operations) PRDI 0000 0100 Reset the Program Enable Latch (Disable Program Operations) RDSR 0000 0101 Read Status Register PRSR 0000 0001 Program Status Register READ 0000 0011 Read from Memory Array beginning at Selected Address PROGRAM 0000 0010 Program Memory Array beginning at Selected Address (32 Bytes) 6685 PGM T04.2 *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. |
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