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X28VC256SM-45 Datasheet(PDF) 5 Page - Xicor Inc. |
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X28VC256SM-45 Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 24 page  X28VC256 5 THE TOGGLE BIT I/O6 Figure 4. Toggle Bit Bus Sequence 3869 FHD F14 Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28VC256 memories that is frequently up- dated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. 3869 FHD F15 LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n X28VC256 READY COMPARE OK? NO YES LAST WRITE YES CE OE WE I/O6 X28VC256 READY VOH VOL LAST WRITE HIGH Z * I/O6 beginning and ending state of I/O6 will vary. * * |
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