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X88C64PI Datasheet(PDF) 6 Page - Xicor Inc. |
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X88C64PI Datasheet(HTML) 6 Page - Xicor Inc. |
6 / 14 page X88C64 6 Toggle Bit Polling RD/WR Control TOGGLE BIT POLLING Because the X88C64 typical nonvolatile write cycle time is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early completion of write. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subse- quent attempts to read the device. When the internal cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. Due to the dual plane architecture, reads for polling must occur in the plane that was written; that is, the state of A12 during a write must match the state of A12 during Toggle Bit Polling. 3867 FHD F09 RD LAST BYTE WRITTEN CE ALE A/D0–A/D7 A8–A12 WR AIN DIN A12=n OPERATION AIN DOUT A12=n AIN DOUT A12=n AIN DOUT A12=n AIN DOUT A12=x AIN ADDR I/O6=X X88C64 READY FOR NEXT OPERATION I/O6=X I/O6=X I/O6=X SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance |
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