3

an authorized service center). The Block Protect con-

figuration is stored in a nonvolatile register, ensuring

that the configuration data will be maintained after the

device is powered-down.

The X88C75 write control input, serves as an external

control over the completion of a previously initiated page

load cycle.

memory characteristics such as byte or page mode write

and Toggle Bit Polling.

Read

A HIGH to LOW transition on ALE latches the address;

the data will be output on the AD pins after either

RD or

Write

A write is performed by latching the addresses on the

falling edge of ALE. The

WR is strobed LOW followed by

data will be latched into the X88C75 on the rising edge

of

WR.

Page Write Operation

The X88C75 supports page mode write operations. This

allows the microcontroller to write from one to thirty-two

bytes of data to the X88C75. Each individual write within

a page write operation must conform to the byte write

timing requirements. The falling edge of

WR starts a

timer delaying the internal programming cycle 100

µs:

therefore, each successive write operation must begin

within 100

µs of the last byte written. The waveform

on page 4 illustrates the sequence and timing

requirements.

PIN DESCRIPTIONS

PIN NAME

I/O

DESCRIPTION

RESET

I

tions. The default active level is HIGH, but it can be reconfigured in EEM register.

PSEN

I

PSEN and holding both RD and WR HIGH. The

STRA, STRB

I/O

The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid

transition on their strobe pins will latch into their port data register the data present at the port input

pins. Writing to an output port data register generates a pulse of fixed duration on its corresponding

strobe pin. The output data presented at the output pins stay valid until the next data is written to the

output port data register.

I/O

The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the

AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select port A I/O mode.

I/O

The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the

BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select port B I/O mode.

I

Non-multiplexed high-order Address Bus inputs for the upper byte of the address.

I/O

Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a HIGH

to LOW transition.

WR

I

During a byte/page write cycle

WR is brought LOW while RD is held HIGH and the data is placed on

the Data Bus. The rising edge of

WR will latch the data into the device.

RD

I

The

latched address. Both

PSEN and WR signals must be held HIGH during RD controlled read

operation.

IRQ

O

The

IRQ is an open-drain output. It can be configured to signal latching of new data into any of the

WC

I

WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to

µs, the time delay from the last

write cycle to the start of internal programming cycle) will inhibit the write operation.

CE

I

The device select (

CE) is an active LOW input. This signal has to be asserted prior to ALE HIGH to

LOW transition in order to generate a valid internal device select signal. Holding this pin HIGH and

ALE LOW will place the device in standby mode. The ports stay active at all times.

ALE

I

2887 PGM T01.1