X25643S8I datasheet(5/16 Pages) XICOR

Part #	X25643S8I

Description	Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM

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Manufacturer	XICOR [Xicor Inc.]

Direct Link	http://www.xicor.com

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5 / 16 page

X25643/45

X25323/25

X25163/65

5

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25

26 27 28 29 30

7

6

5

4

3

2

1

0

DATA OUT

CS

SCK

SI

SO

MSB

HIGH IMPEDANCE

INSTRUCTION

16 BIT ADDRESS

15 14 13

3

2

1

0

7036 FRM 03

For the Page Write Operation (byte or page write) to be

completed, CS can only be brought HIGH after bit 0 of the

last data byte to be written is clocked in. If it is brought

HIGH at any other time, the write operation will not be

completed (Figure 4).

To write to the Status Register, the WRSR instruction is

followed by the data to be written (Figure 5). Data bits 0

and 1 must be “0” .

While the write is in progress following a Status Register

or E2PROM Sequence, the Status Register may be read

to check the WIP bit. During this time the WIP bit will be

high.

RESET/RESET Operation

The RESET (X25xx3) output is designed to go LOW

whenever VCC has dropped below the minimum trip point

and/or the Watchdog timer has reached its programmable

time-out limit.

The RESET (X25xx5) output is designed to go HIGH

whenever VCC has dropped below the minimum trip point

and/or the watchdog timer has reached its programmable

time-out limit.

The RESET/RESET output is an open drain output and

requires a pull up resistor.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS is required to enter an

active state and receive an instruction.

• SO pin is high impedance.

• The Write Enable Latch is reset.

• The Flag Bit is reset.

• Reset Signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent inad-

vertent writes:

• A WREN instruction must be issued to set the Write

Enable Latch.

• CS must come HIGH at the proper clock count in order

to start a nonvolatile write cycle.

Figure 1. Read E2PROM Array Sequence

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