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X25045P Datasheet(PDF) 5 Page - Xicor Inc. |
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X25045P Datasheet(HTML) 5 Page - Xicor Inc. |
5 / 15 page X25043/45 5 Figure 1. Read E2PROM Array Operation Sequence The RESET (X25045) output is designed to go HIGH whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its pro- grammable time-out limit. Operational Notes The X25043/45 powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: • The “write enable” latch is reset upon power-up. • A WREN instruction must be issued to set the “write enable” latch. • CS must come HIGH at the proper clock count in order to start a write cycle. The “write enable” latch is reset when WP is brought LOW. Figure 2. Read Status Register Operation Sequence 0123456789 10 11 12 13 14 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 3844 ILL F15 0123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 3844 FHD F04 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION BYTE ADDRESS 7 6543210 8 9TH BIT OF ADDRESS |
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