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X25057S-2.7 Datasheet(PDF) 2 Page - Xicor Inc. |
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X25057S-2.7 Datasheet(HTML) 2 Page - Xicor Inc. |
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2 / 16 page  X25057 2 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25057 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25057 will be in the standby power mode. CS LOW enables the X25057, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW, nonvolatile writes to the X25057 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25057. If the internal write cycle has already been initiated, WP going low will have no affect on this write. PIN NAMES 7033 FRM T01 PIN CONFIGURATION PRINCIPLES OF OPERATION The X25057 is a 512 x 8 E2PROM designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The X25057 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the WP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume opera- tions where left off. Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage NC No Connect VCC NC SI SCK 7033 FRM F02.1 SO CS VSS WP 1 2 3 4 8 7 6 5 8 Lead MSOP SCK SI VSS WP 7033 FRM F02.2 NC VCC CS SO 1 2 3 4 8 7 6 5 8 Lead TSSOP VCC NC SCK SI 7033 FRM F02 CS SO WP VSS 1 2 3 4 8 7 6 5 8 Lead SOIC/PDIP X25057 X25057 X25057 *0.197" *0.244" 0.120" 0.193" 0.122" 0.252" Not to scale *SOIC Measurement |
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Similar Description - X25057S-2.7 |
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