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X24F128PE Datasheet(PDF) 10 Page - Xicor Inc. |
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X24F128PE Datasheet(HTML) 10 Page - Xicor Inc. |
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10 / 16 page  X24F128 10 Programming to the BL and PPEN Bits A 3 step sequence is required to change the nonvola- tile Block Lock Protect or Program Protect Enable bits: 1) Set PEL=1, Program 00000010 to address FFFFh (Volatile Write Cycle.) 2) Set RPEL=1, Program 00000110 to address FFFFh (Volatile Write Cycle.) 3) Set BL1, BL0, and/or PPEN bits, Program u00xy010 to address FFFFh, where u=PPEN, x=BL1, and y=BL0. (Nonvolatile Write Cycle.) The three step sequence was created to make it diffi- cult to change the contents of the Program Protect Register accidentally. If PEL was set to one by a previous register program operation, the user may start at step 2. RPEL is reset to zero in step 3 so that user is required to perform steps 2 and 3 to make another change. RPEL must be 0 in step 3. If the RPEL bit in the data byte for step 3 is a one, then no changes are made to the Program Protect Register and the device remains at step 2. The PP pin must be LOW or the PPEN bit must be LOW before a nonvolatile register program operation is initiated. Otherwise, the program operation will abort and the device will go into standby mode after the master issues the stop condition in step 3. Step 3 is a nonvolatile write operation, requiring 10mS max to complete (acknowledge polling may be used to reduce this time requirement). It should be noted that step 3 MUST end with a stop condition. If a start condition is issued during or at the end of step 3 (instead of a stop condition) the device will abort the nonvolatile register program and remain at step 2. If the operation is aborted with a start condition, the master must issue a stop to put the device into standby mode. Figure 10. Block Lock Protect Bits and Protected Addresses 7012 FRM T02 Figure 11. PP Pin and PPEN Bit Functionality 7012 FRM T03 BL1 BL0 Protected Addresses Array Location X24F128 0 0 None No Protect 0 1 3000h - 3FFFh Upper 1/4 1 0 2000h - 3FFFh Upper 1/2 1 1 0000h - 3FFFh Full Array PP PPEN Memory Array Not Lock Block Protected Memory Array Block Lock Protected Block Lock Bits PPEN Bit 0 X Programmable Protected Programmable Programmable X 0 Programmable Protected Programmable Programmable 1 1 Programmable Protected Protected Protected |
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