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X24C44DI Datasheet(PDF) 3 Page - Xicor Inc. |
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X24C44DI Datasheet(HTML) 3 Page - Xicor Inc. |
3 / 15 page X24C44 3 DEVICE OPERATION The X24C44 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation. Table 1. contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don’t cares (X) and bits 2 through 0 are the operation codes. The X24C44 requires the instruction to be shifted in with the MSB first. After CE is HIGH, the X24C44 will not begin to interpret the data stream until a logic “1” has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C44 will begin any action. In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. This software or hardware recall operation sets an internal “previous recall” latch. This latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation. WRDS and WREN Internally the X24C44 contains a “write enable” latch. This latch must be set for either writes to the RAM or store operations to the E2PROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and E2PROM stores, effec- tively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up. STO and STORE Either the software STO instruction or a LOW on the STORE input will initiate a transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true: • STO instruction issued or STORE input is LOW. • The internal “write enable” latch must be set (WREN instruction issued). • The “previous recall” latch must be set (either a software or hardware recall operation). Once the store cycle is initiated, all other device func- tions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling condi- tions for store operations. WRITE The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. CE must go LOW before the next rising edge of SK. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. Table 1. Instruction Set Instruction Format, I2 I1 I0 Operation WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and Stores) STO (Figure 3) 1XXXX001 Store RAM Data in E2PROM Reserved 1XXXX010 N/A WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and Stores) RCL (Figure 3) 1XXXX101 Recall E2PROM Data into RAM READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA 3832 PGM T13 X = Don't Care A = Address |
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