Technical Note

BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,

BU9882-W,BU9882F-W,BU9882FV-W

4/22

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2009.04 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

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Synchronous data timing

●

Transmit-only mode

・

After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock

to the VCLK pin.

・

・

SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After

power on, the output data is as follows:

00h address data → 01h address data → 02h address data → …

The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.

When the counter reaches the last address, the next output data is 00h address data. (See Fig. 6)

・

In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Fig. 7)

・

The read operation is in Transmit-Only Mode and can be started after the power is stabilized.

SDA

SCL

D0

ACK

STOP CONDITION

START CONDITION

WRITE DATA(n)

Fig.4 Write Cycle Timing

SCL

WRITE COMMAND

START BIT

STOP BIT

VCLK

SDA

Fig.5 Write Enable Timing

SDA

(IN)

SCL

SDA

(OUT)

t

LOW

Fig.3 Synchronous Data Timing

SDA

SCL

tHD:STA

START BIT

STOP BIT

・

SDA data is latched into the chip at the rising edge of the SCL clock.

・

Output data toggles at the falling edge of the SCL clock.

Fig.6 Transmit Only Mode

Fig.7 Null Bit

10

1

ｔVPU

D7

D6

D5

D4

D3

VCLK

SCL

SDA

Vcc

00h ADDRESS DATA

9

SDA

VCLK

NULL BIT

DATA=1

D0

D1

D7

D6

ADDRESS n

DATA

ADDRESS n+1

DATA

tVPD

tVHIGH tVLOW