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BD8139AEFV Datasheet(PDF) 10 Page - Rohm

Part # BD8139AEFV
Description  High-precision Gamma Correction ICs with built-in DAC
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD8139AEFV Datasheet(HTML) 10 Page - Rohm

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BD8132FV, BD8139AEFV
Technical Note
10/20
www.rohm.com
2009.07 - Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
Auto-read function
The auto-read function enables the IC's 1 kbit microwire type external memory to be automatically read.
This block operates in synchronization with the external input CLK's falling edge to output the external memory chip select
signal CS as well as the memory read data signal MEMDO.
The read data signal consists of a start bit for the external memory, a read code, and a read address. When this signal is sent
to the external memory, the memory outputs the data corresponding to the indicated address. Data output from the memory
is read from the MEMDI pin, and this block automatically generates the serial DATA and LATCH signals and writes the
memory data to the register. Memory reads are synchronized to the CLK's falling edge.
Read addresses start from address 00H and repeat until address 12H, so data must be stored from address 00H to address 12H.
The auto-read function is controlled using the R/W signal. Read access to the external memory is performed continuously
while the R/W signal is low. To access the external memory from another device, the R/W signal must be set to high. When
the R/W signal is set to high, the CS and MEMDO pins enter a high-impedance state.
Fig. 23 Auto-read Timing Chart
Fig. 24 External Memory Data Table
Serial communications timing chart
Auto-read timing chart
Fig.25
Fig.26
SDIN
LATCH
CLK
tLC
tSC
tWL
tWH
tCL
tLA
R/W
C
tRC
tRW
MEMDO
CS
MEMDI
tCDO
tCCS
tDIC
tCR
High-impedance
High-impedance
Auto-read timing
R/W
CS
CLK
MEMDO
Address 00H
Start bit and read code
Address 01H
MEMDI
Memory data
D15 to D0
INTERNAL
DATA
D15 to D0
INTERNAL
LATCH
External m emory data format
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
d16
OSC
mode
Register address
DAC data


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