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A4984SLPTR-T Datasheet(PDF) 4 Page - Allegro MicroSystems |
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A4984SLPTR-T Datasheet(HTML) 4 Page - Allegro MicroSystems |
4 / 21 page DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 4 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Symbol Test Conditions Min. Typ.2 Max. Units Output Drivers Load Supply Voltage Range VBB Operating 8 – 35 V During Sleep Mode 0 – 35 V Logic Supply Voltage Range VDD Operating 3.0 – 5.5 V Output On Resistance RDSON Source Driver, IOUT = –1.5 A – 320 430 mΩ Sink Driver, IOUT = 1.5 A – 320 430 mΩ Body Diode Forward Voltage VF Source Diode, IF = –1.5 A – – 1.3 V Sink Diode, IF = 1.5 A – – 1.3 V Motor Supply Current IBB fPWM < 50 kHz – – 4 mA Operating, outputs disabled – – 2 mA Sleep Mode – – 10 μA Logic Supply Current IDD fPWM < 50 kHz – – 8 mA Outputs off – – 5 mA Sleep Mode – – 10 μA Control Logic Logic Input Voltage VIN(1) VDD0.7 –– V VIN(0) –– VDD0.3 V Logic Input Current IIN(1) VIN = VDD0.7 –20 <1.0 20 μA IIN(0) VIN = VDD0.3 –20 <1.0 20 μA Microstep Select RMS1 MS1 pin – 100 – kΩ RMS2 MS2 pin – 50 – kΩ Logic Input Hysteresis VHYS(IN) As a % of VDD 511 19 % Blank Time tBLANK 0.7 1 1.3 μs Fixed Off-Time tOFF OSC = VDD or GND 20 30 40 μs ROSC = 25 kΩ 23 30 37 μs Reference Input Voltage Range VREF 0–4 V Reference Input Current IREF –3 0 3 μA Current Trip-Level Error3 errI VREF = 2 V, %ITripMAX = 38.27% – – ±15 % VREF = 2 V, %ITripMAX = 70.71% – – ±5 % VREF = 2 V, %ITripMAX = 100.00% – – ±5 % Crossover Dead Time tDT 100 475 800 ns Protection Overcurrent Protection Threshold4 IOCPST 2.1 – – A Thermal Shutdown Temperature TTSD – 165 – °C Thermal Shutdown Hysteresis TTSDHYS –15–°C VDD Undervoltage Lockout VDDUVLO VDD rising 2.7 2.8 2.9 V VDD Undervoltage Hysteresis VDDUVLOHYS –90– mV 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3VERR = [(VREF/8) – VSENSE] / (VREF/8). |
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