11/18

○

Current Read operation allows the master to access data word stored in internal address counter which is

appointed by P1, P0 bit. This operation involves a two-step process. This device will respond with an

acknowledge and then transmit the 8-data bits stored at the addressed location.

If the master does not acknowledge the transmission but does generate the stop condition, at this point this

device discontinues transmission.

note

）If the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output

next address data, and master can't send stop condition, so master can't discontinues transmission.

To stop read command, the master must send no Acknowledge at after D0 output, and issue stop condition.

○

During the sequential read operation, the internal address counter of this device automatically increments with

each acknowledge received ensuring the data from address will be followed with the data from n+1. For read

operations, all bits of the address counter are incremented allowing the entire array to be read during a single

operation. When the counter reaches the top of the array, it will “roll over” to the bottom of the array of BANK

and continue to transmit the data.

○

The sequential read operation can be performed with both current read and random read.

●

PORT1,2,3 access commands

○

Random read operation allows the master to access any memory location of the BANK which is appointed by

P1, P0. This operation involves a two-step process.

First, the master issues a write command which includes the start condition and the slave address field (with

R/W set to “0”) followed by the address of the word be read.

This procedure sets the internal address counter of this device to the desired address.

After the word address acknowledge is received by the master, the master immediately reissues a start

condition followed by the slave address field with R/W the set to “1.”

This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location.

If the master does not acknowledge the transmission but does generate the stop condition, at this point this

device discontinues transmission.

S

T

O

P

P1

0

D7

1

1

0

0

DATA(n)

SDA

LIN

SLAVE

ADDRESS

P0

D0

D0

DATA(n+x）

D7

WPB

R

E

A

D

S

T

A

R

T

Fig.46 SEQUENTIAL READ CYCLE TIMING （PORT0）

Fig.47 RANDOM READ CYCLE TIMING（PORT1～3）

0

0

WA7

1

1

0

0

W

R

I

T

E

S

T

A

R

T

R

/

W

1st WORD

ADDRESS(n)

SDA

LINE

SLAVE

ADDRESS

0

WA0

A

C

K

A

C

K

0

0

1

1

0

0

R

E

A

D

S

T

A

R

T

R

/

W

SLAVE

ADDRESS

0

A

C

K

D7

DATA(n)

D0

A

C

K

S

T

O

P

WPB

Fig.48 CURRENT READ CYCLE TIMING

（PORT1～3）

0

1

1

0

0

R

E

A

D

S

T

A

R

T

R

/

W

SDA

LINE

SLAVE

ADDRESS

A

C

K

D7

DATA

D0

A

C

K

S

T

O

P

0

0

WPB