Low-Cost, µP Supervisory Circuits

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5

______________________________________________________________Pin Description

Watchdog Output pulls low when the internal watch-

dog timer finishes its 1.6sec count and does not go

high again until the watchdog is cleared. WDO also

below the reset threshold, WDO stays low; however,

unlike RESET, WDO does not have a minimum pulse

old, WDO goes high with no delay.

Active-High Reset Output is the inverse of RESET.

Whenever RESET is high, RESET is low, and vice

versa (Figure 2). The MAX813L has a RESET output

only.

Active-Low Reset Output pulses low for 200ms when

reset threshold (4.65V in the MAX705 and 4.40V in the

above the reset threshold or MR goes from low to high

(Figure 3). A watchdog timeout will not trigger RESET

unless WDO is connected to MR.

Watchdog Input. If WDI remains high or low for

1.6sec, the internal watchdog timer runs out and

WDO goes low (Figure 1). Floating WDI or connect-

ing WDI to a high-impedance three-state buffer dis-

ables the watchdog feature. The internal watchdog

timer clears whenever reset is asserted, WDI is three-

stated, or WDI sees a rising or falling edge.

Power-Fail Output goes low and sinks current when

PFI is less than 1.25V; otherwise PFO stays high.

Power-Fail Voltage Monitor Input. When PFI is less

than 1.25V, PFO goes low. Connect PFI to GND or

FUNCTION

MAX705/MAX706

RESET

7

8

—

WDO

8

—

8

RESET

—

7

7

No Connect

N.C.

—

6

—

WDI

6

—

6

PFO

5

5

5

PFI

4

4

4

0V Ground Reference for all signals

GND

3

3

3

+5V Supply Input

2

2

2

NAME

DIP/SO

DIP/SO

DIP/SO

MAX707/MAX708

PIN

—

2

1

—

8

7

6

5

4

µMAX

2

—

1

—

—

7

6

5

4

µMAX

1

2

—

—

8

7

6

5

4

µMAX

MAX813L

Manual-Reset Input triggers a reset pulse when

pulled below 0.8V. This active-low input has an inter-

nal 250µA pull-up current. It can be driven from a TTL

or CMOS logic line as well as shorted to ground with

a switch.

MR

1

1

1

3

3

3