Synchronous Buck Controller with Constant On-Time and Valley Current Mode ( 44 Page)
Rev. 0 | Page 19 of 44
THEORY OF OPERATION
The ADP1870/ADP1871 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by utilizing valley
current-mode control architecture. This allows the ADP1870/
ADP1871 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.
The ADP1870/ADP1871 have an internal regulator (VREG) for
biasing and supplying power for the integrated MOSFET drivers.
A bypass capacitor should be located directly across the VREG
(Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence
is the biasing of the current-sense amplifier, the current-sense
gain circuit (see the
Programming Resistor (RES) Detect Circuit
section), the soft start circuit, and the error amplifier.
The current-sense blocks provide valley current information
Programming Resistor (RES) Detect Circuit
and are a variable of the compensation equation for loop stability
section). The valley current
information is extracted by forcing 0.4 V across the DRVL output
and PGND pin, which generates a current depending on the
resistor across DRVL and PGND in a process performed by the
RES detect circuit. The current through the resistor is used to set
the current-sense amplifier gain. This process takes approximately
800 μs, after which the drive signal pulses appear at the DRVL
and DRVH pins synchronously and the output voltage begins to
rise in a controlled manner through the soft start sequence.
The rise time of the output voltage is determined by the soft
start and error amplifier blocks (see the
the beginning of a soft start, the error amplifier charges the
external compensation capacitor, causing the COMP/EN pin to
rise above the enable threshold of 285 mV, thus enabling the
The ADP1870/ADP1871 have digital soft start circuitry, which
involves a counter that initiates an incremental increase in current,
by 1 μA, via a current source on every cycle through a fixed internal
capacitor. The output tracks the ramping voltage by producing
PWM output pulses to the upper-side MOSFET. The purpose is to
limit the in-rush current from the high voltage input supply (V
to the output (V
PRECISION ENABLE CIRCUITRY
The ADP1870/ADP1871 employ precision enable circuitry. The
enable threshold is 285 mV typical with 35 mV of hysteresis.
The devices are enabled when the COMP/EN pin is released,
allowing the error amplifier output to rise above the enable
). Grounding this pin disables the
ADP1870/ADP1871, reducing the supply current of the devices
to approximately 140 μA. For more information, see
Figure 66. Release COMP/EN Pin to Enable the ADP1870/ADP1871
HICCUP MODE INITIALIZED
MAXIMUM CURRENT (UPPER CLAMP)
USABLE RANGE ONLY AFTER SOFT START
PERIOD IF CONTUNUOUS CONDUCTION
MODE OF OPERATION IS SELECTED.
PRECISION ENABLE THRESHOLD
Figure 67. COMP/EN Voltage Range
The undervoltage lockout (UVLO) feature prevents the part from
operating both the upper- and lower-side MOSFETs at extremely
low or undefined input voltage (V
) ranges. Operation at an
undefined bias voltage may result in the incorrect propagation
of signals to the high-side power switches. This, in turn, results
in invalid output behavior that can cause damage to the output
devices, ultimately destroying the device tied at the output. The
UVLO level has been set at 2.65 V (nominal).
ON-BOARD LOW DROPOUT REGULATOR
The ADP1870 uses an on-board LDO to bias the internal digital
and analog circuitry. With proper bypass capacitors connected
to the VREG pin (output of internal LDO), this pin also provides
power for the internal MOSFET drivers. It is recommended to
float VREG if VIN is utilized for greater than 5.5 V operation.
The minimum voltage where bias is guaranteed to operate is
2.75 V at VREG.
For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended that
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