2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer ( 12 Page)
Rev. 0 | Page 10 of 12
PCB LAYOUT CONSIDERATIONS
The ADCLK944 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important to
use low impedance supply planes for both the negative supply
) and the positive supply (V
) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
The following references to the ground plane assume that the V
power plane is grounded for LVPECL operation. Note that, for
ECL operation, the V
power plane becomes the ground plane.
It is also important to adequately bypass the input and output
supplies. Place a 1 μF electrolytic bypass capacitor within several
inches of each V
power supply pin to the ground plane. In
addition, place multiple high quality 0.001 μF bypass capacitors
as close as possible to each V
supply pin, and connect the
capacitors to the ground plane with redundant vias. Select high
frequency bypass capacitors for minimum inductance and ESR.
To improve the effectiveness of the bypass at high frequencies,
minimize parasitic layout inductance. Also, avoid discontinuities
along input and output transmission lines; such discontinuities
can affect jitter performance.
In a 50 Ω environment, input and output matching have a signif-
icant impact on performance. The buffer provides internal 50 Ω
termination resistors for both the CLK and CLK inputs. Normally,
the return side is connected to the reference pin that is provided.
Bypass the termination potential using ceramic capacitors to
prevent undesired aberrations on the input signal due to parasitic
inductance in the termination return path. If the inputs are dc-
coupled to a source, take care to ensure that the pins are within
the rated input differential and common-mode voltage ranges.
If the return is floated, the device exhibits a 100 Ω cross-termi-
nation, but the source must then control the common-mode
voltage and supply the input bias currents.
ESD/clamp diodes between the input pins prevent the application
from developing excessive offsets to the input transistors. ESD
diodes are not optimized for best ac performance. When a clamp
is required, it is recommended that appropriate external diodes
Exposed Metal Paddle
The exposed metal paddle on the ADCLK944 package is both an
electrical connection and a thermal enhancement. For the device
to function properly, the paddle must be properly attached to
When properly mounted, the ADCLK944 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK944. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
from the top layer of the PCB down to the V
power plane (see
). The ADCLK944 evaluation board (ADCLK944/PCBZ)
provides an example of how to attach the part to the PCB.
VIAS TO V
Figure 17. PCB Land for Attaching Exposed Paddle
Sponsor of Alldatasheet
Alldistributor will be your best source to find out the prices for your daily purchasing of Electronic Components.
World wide Buy/Sell Semiconductor & Electronic components on-line marketplace for Brokers and Distributors.
Korean Buy/Sell Semiconductor & Electronic components on-line marketplace for Brokers and Distributors.
Chinese Marketplace to Buy/Sell Semiconductor Electronic components on-line for Brokers and Distributors.
Japanese Buy/Sell Semiconductor & Electronic components on-line marketplace for Brokers and Distributors.
Does ALLDATASHEET help your business so far?
[ DONATE ]
All Rights Reserved©
2003 - 2013
|   Chinese :
| German :
| Japanese :
| Russian :
| Spanish :
| French :
| Italian :
| Portuguese :
| Polish :