Part Name
         Description
ADCLK944BCPZ-WP

 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer ( 12 Page)


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ADCLK944
Rev. 0 | Page 6 of 12
1. EXPOSED PAD MUST BE CONNECTED
TO VEE.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
Q1
NOTES
Q1
Q2
9
Q2
1
3
4
CLK
VREF
2
VT
CLK
TOP VIEW
(Not to Scale)
ADCLK944
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Differential Input (Positive).
2
VT
Center Tap. This pin provides the center tap of a 100 Ω input resistor for the CLK and CLK inputs.
3
VREF
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.
4
CLK
Differential Input (Negative).
5, 16
VEE
Negative Supply Pin.
6, 7
Q3, Q3
Differential LVPECL Outputs.
8, 13
VCC
Positive Supply Pin.
9, 10
Q2, Q2
Differential LVPECL Outputs.
11, 12
Q1, Q1
Differential LVPECL Outputs.
14, 15
Q0, Q0
Differential LVPECL Outputs.
EPAD
The exposed pad must be connected to VEE.



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