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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2305B

3.3VZERODELAYCLOCKBUFFER

JANUARY 2010

2010

Integrated Device Technology, Inc.

DSC 6994/5

c

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five outputs

• Zero Input-Output Delay

• Output Skew < 250ps

• Low jitter <175 ps cycle-to-cycle

• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)

• IDT2305B-1 for Standard Drive

• IDT2305B-1H for High Drive

• No external RC network required

• Power down mode

• Available in SOIC and TSSOP packages

FUNCTIONAL BLOCK DIAGRAM

IDT2305B

3.3V ZERO DELAY

CLOCK BUFFER

DESCRIPTION:

The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts

one reference input, and drives out five low skew clocks. The -1H version

of this device operates, up to 133MHz frequency and has a higher drive

than the -1 device. All parts have on-chip PLLs which lock to an input clock

on the REF pin. The PLL feedback is on-chip and is obtained from the

CLKOUT pad. In the absence of an input clock, the IDT2305B enters power

tri-stated, and the PLL is not running, resulting in a significant reduction of

power.

The IDT2305B is characterized for both Industrial and Commercial

operation.

PLL

8

CLK1

CLK2

CLK3

CLK4

Control

Logic

REF

CLKOUT

1

3

2

5

7

NOTE: EOL for non-green parts to occur on 5/13/10 per

PDN U-09-01