C

CT

S

OSC

Q

CS

R

PWM

Q

PWM

V

GD

C

C

3.33 V

1.67 V

1 V

70%

ON

30%

OFF

CS Signal Dominant

Maximum Duty Cycle Dominant

R

OSC

UDG-10006

TPS92001, TPS92002

www.ti.com

SLUSA24 – FEBRUARY 2010

Figure 2. Oscillator Latch and PWM Latch Waveforms

Figure 2 shows the waveforms associated with the oscillator latch and the PWM latch (shown in the Typical

N-channel MOSFET on the CS pin causing any external capacitance used for leading edge blanking connected

to this pin to be discharged to ground. By discharging any external capacitor completely to ground during the

external switch off-time, the noise immunity of the converter is enhanced allowing the user to design in smaller

R-C components for leading edge blanking. A high CLK signal also sets the level sensitive S input of the PWM

during soft-start or if the SS pin is disabled.

trips the 1-V threshold while CLK is low. If the CS signal does not cross the 1-V threshold while CLK is low, the

GD signal will be dominated by the maximum duty cycle programmed by the user. Figure 2 illustrates the various

waveforms for a design set up for a maximum duty cycle of 70%.

4.32 k

external timing resistors, resulting in minimal change in frequency over temperature. Because of the oscillator

susceptibility to capacitive coupling, examine the oscillator frequency by looking at the common RTC-RTD-CT

node on the circuit board as opposed to looking at pins 3 and 4 directly. For good noise immunity, the RTC and

RTD resistors should be placed as close to pins 3 and 4 of the device as possible. The timing capacitor should

be returned directly to the ground pin of the device with minimal stray inductance and capacitance.

Copyright © 2010, Texas Instruments Incorporated

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