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15 page 
t td S ta MSB OUT BIT 6 . . . 1 LSB OUT t sck t Lead t Lag twsck t wsck tr tf tv tho tdis MSB IN BIT 6 . . . 1 LSB IN thi tsu SS SCLK MISO MOSI www.ti.com SLOS631 – MARCH 2010 SPI Interface Timing Figure 9. SPI Interface Timing Diagram Timing Requirements (See Figure 9) At 25°C, DVdd = 1.8V Table 6. SPI Interface Timing PARAMETER TEST CONDITION IOVDD=1.8V IOVDD=3.3V UNITS MIN TYP MAX MIN TYP MAX tsck SCLK Period 100 50 ns tsckh SCLK Pulse width High 50 25 ns tsckl SCLK Pulse width Low 50 25 ns tlead Enable Lead Time 30 20 ns tlag Enable Lag Time 30 20 ns td;seqxfr Sequential Transfer Delay 40 20 ns ta Slave DOUT access time 40 20 ns tdis Slave DOUT disable time 40 25 ns tsu DIN data setup time 15 10 ns th;DIN DIN data hold time 15 10 ns tv;DOUT DOUT data valid time 45 25 ns tr SCLK Rise Time 4 4 ns tf SCLK Fall Time 4 4 ns Copyright © 2010, Texas Instruments Incorporated 15 Product Folder Link(s): TLV320AIC3253 |
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