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MAX1065 Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1065 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 14 page During the acquisition, the analog input (AIN) charges capacitor CDAC. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CDAC represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node ZERO to zero within the limits of 14-bit resolution. At the end of the conversion, force CS low to put valid data on the bus. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calcu- late acquisition time: tACQ = 11(RS + RIN) x 35pF where RIN = 800Ω, RS = the input signal’s source impedance, and tACQ is never less than 1.1µs. A source impedance less than 1kΩ does not significantly affect the ADC’s performance. To improve the input-signal bandwidth under AC condi- tions, drive AIN with a wideband buffer (>4MHz) that can drive the ADC’s input capacitance and settle quickly. Power-Down Modes Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see Selecting Standby or Shutdown Mode section). The MAX1065/ MAX1066 automatically enter either standby mode, ref- erence and buffer on, or shutdown, reference and buffer off, after each conversion depending on the sta- tus of R/C during the second falling edge of CS. Internal Clock The MAX1065/MAX1066 generate an internal conver- sion clock. This frees the microprocessor from the bur- den of running the SAR conversion clock. Total conversion time after entering hold mode (second falling edge of CS) to end-of-conversion (EOC) falling is 4.7µs (max). Applications Information Starting a Conversion CS and R/C control acquisition and conversion in the MAX1065/MAX1066 (Figure 2). The first falling edge of CS powers up the device and puts it into acquisition mode if R/C is low. The convert start is ignored if R/C is high. When powering up from shutdown, the MAX1065/ MAX1066 needs at least 10ms (CREFADJ = 0.1µF, CREF = 1µF) for the internal reference to wake up and settle before starting the conversion. The ADC may wake up from shutdown to an unknown state. Put the ADC in a known state by completing one “dummy” conversion. The MAX1065/ MAX1066 will be in a known state, ready for actual data acquisition, after the completion of the dummy conversion. A dummy conversion consists of one full conversion cycle. The MAX1065 provides an alternative reset function to reset the device (see RESET section). Selecting Standby or Shutdown Mode The MAX1065/MAX1066 have a selectable standby or low-power shutdown mode. In standby mode, the ADC’s internal reference and reference buffer do not power down between conversions, eliminating the need to wait for the reference to power up before performing the next conversion. Shutdown mode powers down the reference and reference buffer after completing a con- version. Supply current is greatly reduced when in shutdown mode. The reference and reference buffer require a minimum of 10ms (CREFADJ = 0.1µF, CREF = 1µF) to power up and settle from shutdown. The state of R/C at the second falling edge of CS selects which power-down mode the MAX1065/ MAX1066 enters upon conversion completion. Holding R/C low causes the MAX1065/MAX1066 to enter stand- by mode. The reference and buffer are left on after the conversion completes. R/C high causes the MAX1065/MAX1066 to enter shutdown mode and shut down the reference and buffer after conversion (Figures 5 and 6). When using an external reference, set the REF power- down bit high for lowest current operation. Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface _______________________________________________________________________________________ 9 ANALOG INPUT D0–D7 OR D8–D13 EOC REFADJ REF DGND AGND HBEN CS R/C AIN AVDD DVDD MAX1066 0.1 μF 0.1 μF 5V ANALOG 5V DIGITAL 0.1 μF1μF μP DATA BUS HIGH BYTE LOW BYTE Figure 3. Typical Application Circuit for MAX1066 |
Similar Part No. - MAX1065_09 |
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Similar Description - MAX1065_09 |
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