MAX793_CSE datasheet(4/20 Pages) MAXIM

Part #	MAX793_CSE

Description	3.0V/3.3V Adjustable Microprocessor Supervisory Circuits

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Manufacturer	MAXIM [Maxim Integrated Products]

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3.0V/3.3V Adjustable Microprocessor

Supervisory Circuits

4

_______________________________________________________________________________________

CONDITIONS

VOL

V

VOL

V

ISINK = 3.2mA, VCC = VRST max

MAX79_E, VBATT = VCC = 1.2V, ISINK = 200µA

BATT ON Output-

Voltage Low

MAX79_C, VBATT = VCC = 1.0V, ISINK = 40µA

0.2VCC

RESET Output-Voltage Low

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

VIL

V

tMR

ns

MAX793/MAX794 only

VRST max < VCC < 5.5V

MR Pulse Width

100

All Inputs Including PFO

(Note 10)

0.3VCC

VIH

0.7VCC

0.17

0.3

0.13

0.3

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the

MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

tMD

ns

MAX793/MAX794 only, MR = 0V

MAX793/MAX794 only

µA

MR-to-Reset Delay

25

70

250

MR Pullup Current

75

250

Ω

ns

VCC = VRST max, Figure 9

Enable mode, VCC = VRST max

CE IN-to-CE OUT

Propagation Delay

Disable mode

27

CE IN-to-CE OUT

Resistance

VOH

VOL

V

VCC = VRST max, IOUT = 1.6mA,

V CE IN = 0V

VCC = VRST max, IOUT = -1mA,

V CE IN = VCC

CE OUT Drive from CE IN

0.2VCC

0.8VCC

nA

46

ILEAK

±10

CE IN Leakage Current

Note 1: VCC supply current, logic-input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),

PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at VBATT = 3.6V and VCC =

5.5V. The state of RESET is tested at VCC = VCC min.

Note 2: Tested at VBATT = 3.6V, VCC = 3.5V and 0V. The battery current rises to 10µA over a narrow transition window around VCC

= 1.9V.

Note 3: Leakage current into the battery is tested under the worst-case conditions at VCC = 5.5V, VBATT = 1.8V and VCC = 1.5V,

VBATT = 1.0V.

Note 4: Guaranteed by design.

Note 5: When VSW > VCC > VBATT, OUT remains connected to VCC until VCC drops below VBATT. The VCC-to-VBATT comparator

has a small 15mV typical hysteresis to prevent oscillation. For VCC < 1.75V (typical), OUT switches to BATT regardless of

VBATT.

Note 6: When VBATT > VCC > VSW, OUT remains connected to VCC until VCC drops below the battery switch threshold (VSW).

Note 7: OUT switches from BATT to VCC when VCC rises above the reset threshold, if VBATT > VRST. In this case, switchover back

to VCC occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If

VBATT < VRST, OUT switches from BATT to VCC when VCC exceeds VBATT.

Note 8: The reset threshold tolerance is wider for VCC rising than for VCC falling to accommodate the 10mV typical hysteresis,

which prevents internal oscillation.

Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).

Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.

µs

10

Reset to CE OUT High Delay

tWD

s

0V < VCC < 5.5V

Watchdog Timeout Period

IOH = 500µA, VCC < 2.3V

µA

1.00

1.60

2.25

-1

0.01

1

WDI Input Current

V

VOH

0.8VBATT

CE OUT Output-Voltage

High (reset active)

ns

WDI Pulse Width

100

MANUAL RESET INPUT

CHIP-ENABLE GATING

WATCHDOG (MAX793/MAX794 only)

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