+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 5

TIMING CHARACTERISTICS

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 7: Sample tested to 0.1% AQL.

Note 8: External load should not change during conversion for specified accuracy.

Note 10: Guaranteed by design. Not subject to production testing.

Note 11: The MAX148 typically draws 400FA less than the values shown.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Acquisition Time

1.5

μs

DIN to SCLK Setup

100

ns

DIN to SCLK Hold

0

ns

SCLK Fall to Output Data Valid

Figure 1

MAX14_ _C/E

20

200

ns

MAX14_ _M

20

240

CS Fall to Output Enable

Figure 1

240

ns

CS Rise to Output Disable

Figure 2

240

ns

CS to SCLK Rise Setup

100

ns

CS to SCLK Rise Hold

0

ns

SCLK Pulse Width High

200

ns

SCLK Pulse Width Low

200

ns

SCLK Fall to SSTRB

Figure 1

240

ns

CS Fall to SSTRB Output Enable

External clock mode only, Figure 1

240

ns

CS Rise to SSTRB Output Disable

External clock mode only, Figure 2

240

ns

SSTRB Rise to SCLK Rise

Internal clock mode only (Note 7)

0

ns