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VG37648041AT Datasheet(PDF) 4 Page - Vanguard International Semiconductor |
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VG37648041AT Datasheet(HTML) 4 Page - Vanguard International Semiconductor |
4 / 86 page Document : 1G5-0157 Rev.1 Page 4 VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM FUNCTIONAL BLOCK DIAGRAM- X4 CONFIGURATION CKE CLK# Generator CLK CS# WE# CAS# RAS# LOGIC MODE REGISTERS REFRESH COUNTER 13 ROW- ADDRESS MUX BANK0 ROW- ADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8192x1024x8) SENSE AMPLIFIERS BANK0 MEMORY ARRAY (8192x1024x8) SENSE AMPLIFIERS BANK1 BANK2 BANK3 13 I/O GATING DM MASK LOGIC COLUMN DECODER BANK0 COLUMN ADDRESS CONTROL LOGIC COUNTER/ LATCH 10 COL0 ADDRESS RESGISTER 15 A0-A12 BA0-BA1 2 11 13 13 2 READ LATCH MUX 8 WRITE FIFO & DRIVERS 8 8 4 4 ctk out in ctk CLK DQS GENERATOR DRVRS DLL CLK 1 DOS COL0 4 2 8 MASK DATA 1 1 4 4 1 1 4 4 1 4 RCVRS COL0 DO0 DQ3,DM DQS 1 1 Note 1: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not necessarily represent an actual circuit implementation. Note 2: DM is a unidirectional signal (input only) but is internally loaded to match the load of the bidirectional DQ and DQS signals. (x8) INPUT REGISTERS DATA |
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