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VG3617801BT-8H Datasheet(PDF) 10 Page - Vanguard International Semiconductor |
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VG3617801BT-8H Datasheet(HTML) 10 Page - Vanguard International Semiconductor |
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10 / 68 page  Document:1G5-0133 Rev.1 Page 10 VIS VG3617801CT 16Mb CMOS Synchronous Dynamic RAM Current state CS RAS CA WE Address Command Action Notes Read with auto precharge H X X X X DESL Continue burst to L H H H X NOP Continue burst to L H H L X BST ILLEGAL L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 WRIT/WRITA ILLEGAL L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X PEF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Write with auto precharge H X X X X DESL Continue burst to recovering with auto precharge L H H H X NOP Continue burst to recovering with auto precharge L H H L X BST ILLEGAL L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 WRIT/WRITA ILLEGAL L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-code MRS ILLEGAL Precharging H X X X X DESL idle after tRP L H H H X NOP idle after tRP L H H L X BST idle after tRP L H L H BA,CA,A10 READ/READA ILLEGAL 3 L H L L BA,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BA,RA ACT ILLEGAL 3 L L H L BA,A10 PRE/PALL idle after tRP L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Row activating H X X X X DESL row active after tRCD L H H H X NOP row active after tRCD L H H L X BST row active after tRCD L H L H BA,CA,A10 READ/READA ILLEGAL 3 L H L L BA,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BA,RA ACT ILLEGAL 3,10 L L H L BA,A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL end Prech ing arg → end Prech ing arg → end Write → end Write → Nop Enter → Nop Enter → Nop Enter → Nop Enter → Nop Enter → Nop Enter → Nop Enter → (2/3) |
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