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VG26S18165CJ-5 Datasheet(PDF) 10 Page - Vanguard International Semiconductor |
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VG26S18165CJ-5 Datasheet(HTML) 10 Page - Vanguard International Semiconductor |
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10 / 27 page  Document:1G5-0147 Rev.1 Page 10 VIS VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM AC Characteristics ( Ta = 0 to + 70°C, Vcc = 5V % or 3.3V %, Vss = 0V) *1, *2, *3, *4, *5 Test conditions • Output load: two TTL Loads and 50pF (VCC = 5.0V %) one TTL Load and 50pF (VCC = 3.3V %) • Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V %) • Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V %, 3.3V %) 10 ± 10 ± 10 ± 10 ± 10 ± 10 ± 10 ± 10 ± Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) Parameter Symbol VG26(V)(S) 18165C Unit Notes -5 -6 Min Max Min Max Random read or write cycle time tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns LCAS / UCAS precharge time in normal mode tCPN 10 - 10 - ns RAS pulse width tRAS 50 10000 60 10000 ns 6 LCAS / UCAS pulse width tCAS 8 10000 10 10000 ns 7 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 8 - 10 - ns Column address setup time tASC 0 - 0 - ns 8 Column address hold time tCAH 8 - 10 - ns RAS to LCAS / UCAS delay time tRCD 12 37 14 45 ns 9 RAS to column address delay time tRAD 10 25 12 30 ns 10 Column address to RAS lead time tRAL 25 - 30 - ns RAS hold time tRSH 8 - 10 - ns LCAS / UCAS hold time tCSH 38 - 40 - ns LCAS / UCAS to RAS precharge time tCRP 5 - 5 - ns 11 OE to Din delay time tOED 12 - 15 - ns Transition time (rise and fall) tT 1 50 1 50 ns 12 Refresh period tREF - 16 - 16 ms Refresh period (S- Version) tREF - 128 - 128 ms LCAS / UCAS to output in Low- Z tCLZ 0 - 0 - ns LCAS / UCAS delay time from Din tDZC 0 - 0 - ns OE delay time from Din tDZO 0 - 0 - ns |
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