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VT83205Q Datasheet(PDF) 2 Page - Vaishali Semiconductor |
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VT83205Q Datasheet(HTML) 2 Page - Vaishali Semiconductor |
2 / 4 page VT83205 2001-03-08 Page 2 MDST-0001-01 www.vaishali.com Vaishali Semiconductor 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063 Figure 2. Pin Configuration Table 1. Pin Description Name Pin # Type Description X1 1 XI Crystal connection. Connect to a pullable crystal of 10–14.318 MHz VDD1 2,3 P Core VDD. Connect to 3.3V VIN 4 I Voltage input to VCXO. Zero to 3V signal controls the frequency of the VCXO. GND 5,6,13 P Connect to ground. S2 7 I Select input #2. Selects outputs per Table 2 OE 8 I Active HIGH Output enable . Outputs in Hi-Z state when LOW CLK1 9 O Clock output #1 per Table 2. SO 10 I Select input #0. Selects output per Table 2 VDD2 11 P Output VDD. Connect to 3.3V CLK2 12 O Clock output #2 per Table 2 S1 14 I Select input #1. Selects outputs per Table 2 NC 15 - There is no internal connection to this pin. X2 16 XO Crystal connection. Connect to a pullable crystal of 10 MHz – 14.318 MHz. Legend: I = Input O = Output P = Power supply connection XI, XO = Crystal connections. Table 2. Pullable Crystal Specifications Parameter Value Correlation (load) capacitance 30 pF C0/C1 240 max ESR 35 Ω max Operating Temperature 0 °C to +70°C Initial Accuracy ±20 ppm Temperature + Aging Stability ±50 ppm VT83205 Pinout VDD2 VDD1 GND GND CLK2 CLK1 X1 VDD1 VIN GND S2 NC S1 S0 OE X2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 |
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