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HY27UH08AG5M Datasheet(PDF) 5 Page - Hynix Semiconductor |
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HY27UH08AG5M Datasheet(HTML) 5 Page - Hynix Semiconductor |
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5 / 49 page  Rev. 0.6 / Dec. 2006 HY27UH08AG(5/D)M Series 16Gbit (2Gx8bit) NAND Flash 1. SUMMARY DESCRIPTION The HYNIX HY27UH08AG(5/D)M series is a 2Gx8bit with spare 64Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 16,384 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block. Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modifying can be locked using the WP input pin. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi- ple memories the R/B pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27UH08AG(5/D)M extended reliability of 100K pro- gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. This device includes also extra features like OTP/Unique ID area, Read ID2 extension. The HYNIX HY27UH08AG(5/D)M series is available in 48 - TSOP1 12 x 20 mm, 52 - TLGA 12X17mm. 1.1 Product List 2. BUS OPERATION PART NUMBER ORIZATION VCC RANGE PACKAGE HY27UH08AG5M x8 2.7V - 3.6 Volt 48TSOP1 HY27UH08AGDM x8 2.7V - 3.6 Volt 52TLGA |
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