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27 page 
Rev. 1.0 /Nov. 2007 27 HY5DU56822F(L)TP HY5DU561622F(L)TP CAPACITANCE (TA=25oC, f=100MHz) Note: 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Parameter Pin Symbol Min Max Unit Input Clock Capacitance CK, /CK CI1 2.0 3.0 pF Delta Input Clock Capacitance CK, /CK Delta CI1 - 0.25 pF Input Capacitance All other input-only pins CI1 2.0 3.0 pF Delta Input Capacitance All other input-only pins Delta CI2 - 0.5 pF Input / Output Capacitance DQ, DQS, DM CIO 4.0 5.0 pF Delta Input / Output Capacitance DQ, DQS, DM Delta CIO - 0.5 pF VREF VTT RT=50 Ω Zo=50 Ω CL=30pF Output |
