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HY5DU323222QP-6 Datasheet(PDF) 3 Page - Hynix Semiconductor

Part # HY5DU323222QP-6
Description  32M(1Mx32) DDR SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5DU323222QP-6 Datasheet(HTML) 3 Page - Hynix Semiconductor

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Rev. 0.3 / Jun. 2005
3
1HY5DU323222QP
DESCRIPTION
The Hynix HY5DU323222 is a 33,554,432-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 1Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•VDD, VDDQ = 2.5V
± 5%
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 20mm x 14mm 100pin LQFP with
0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 3 and 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
ORDERING INFORMATION
Note) Hynix supports lead free part for each speed grade with same specification, except lead free material.
We’ll add “P” character after “Q” for lead free product.
Part No.
Power Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DU323222QP-5
VDD/VDDQ = 2.5V
200MHz
400Mbps/pin
SSTL_2
20mm x 14mm
100pin LQFP
HY5DU323222QP-6
166MHz
333Mbps/pin
Rev. 0.2 / May. 2004
3


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