Rev. 1.0 / Aug. 2009

2

Synchronous DRAM Memory 128Mbit (8Mx16bit)

H57V1262GFR Series

DESCRIPTION

The Hynix H57V1262GFR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica-

tions which require wide data I/O and high bandwidth. H57V1262GFR series is organized as 4banks of 2,097,152 x 16.

H57V1262GFR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs

are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high

bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-

quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

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This product is in compliance with the directive pertaining of RoHS.

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

H57V1262GFR-50X

200MHz

4Banks x 2Mbits

x16

LVTTL

54 Ball FBGA

H57V1262GFR-60X

166MHz

H57V1262GFR-70X

143MHz

H57V1262GFR-75X

133MHz

•

Voltage: VDD and VDDQ 3.3V supply voltage

•

All device pins are compatible with LVTTL interface

•

54 Ball FBGA (Lead or Lead Free Package)

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by UDQM, LDQM

•

Internal four banks operation

•

Auto refresh and self refresh

•

4096 Refresh cycles / 64ms

•

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

Programmable CAS Latency; 2, 3 Clocks

•

Burst Read Single Write operation

•

Operation temperature