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H5RS5223CFR-18C Datasheet(PDF) 6 Page - Hynix Semiconductor |
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H5RS5223CFR-18C Datasheet(HTML) 6 Page - Hynix Semiconductor |
6 / 66 page Rev.1.5 / Jul. 2008 6 H5RS5223CFR BALLOUT DESCRIPTIONS FBGA BALLOUT SYMBOL TYPE DESCRIPTION J10, J11 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and con- trol input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. H4 CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the inter- nal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. F9 CS# Input Chip Select: CS# enables (registered LOW)and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. H3, F4, H9 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE#(along with CS#) define the command being entered. E(3, 10), N(3, 10) DM0-DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on rising and falling edges of WDQS. G(4, 9), H10 BA0 - BA2 Input Bank Address Inputs: BA0 and BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. H(2, 11), K(2-4, 9-11), L(4, 9), M(4, 9) A0-A11 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit(A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command deter- mines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0 - BA2 ) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER com- mand. B(2, 3), C(2, 3), E2, F(2, 3), G3,B(10, 11), C(10, 11), E11, F(10, 11), G10, L10, M(10, 11), N11, R(10, 11), T(10,11), L3, M(2, 3), N2,R(2, 3), T(2, 3) DQ0-31 I/O Data Input/Output: D(3, 10), P(3, 10) RDQS0-3 Output READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. D(2, 11), P(2, 11) WDQS0-3 Input WRITE Data strobe: Input with write data. WDQS is center aligned to the input data. U4 SEN Input Scan Enable Pin. Logic High would enable Scan Mode. Should be tied to GND when not in use. This pin is a CMOS input. J(2, 3) NC/RFU No Connect |
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