HYMD132725BL8-H datasheet(10/17 Pages) HYNIX

Part #	HYMD132725BL8-H

Description	Unbuffered DDR SDRAM DIMM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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10 / 17 page

Rev. 0.3/May. 02

10

HYMD132725B(L)8-M/K/H/L

- continued -

Parameter

Symbol

DDR266(2-2-2)

DDR266A

DDR266B

DDR200

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Input Setup Time (fast slew rate)

tIS

0.9

-

0.9

-

0.9

-

1.1

-

ns

2,3,5,6

Input Hold Time (fast slew rate)

tIH

0.9

-

0.9

-

0.9

-

1.1

-

ns

2,3,5,6

Input Setup Time

(slow slew rate)

tIS

1.0

-

1.0

-

1.0

-

1.1

-

ns

2,4,5,6

Input Hold Time (slow slew rate)

tIH

1.0

-

1.0

-

1.0

-

1.1

-

ns

2,4,5,6

Input Pulse Width

tIPW

2.2

2.5

-

ns

6

Write DQS High Level Width

tDQSH

0.35

-

0.35

-

0.35

-

0.35

-

CK

Write DQS Low Level Width

tDQSL

0.35

-

0.35

-

0.35

-

0.35

-

CK

Clock to First Rising edge of

DQS-In

tDQSS

0.72

1.28

0.75

1.25

0.75

1.25

0.75

1.25

CK

Data-In Setup Time to DQS-In

(DQ & DM)

tDS

0.5

-

0.5

-

0.5

-

0.6

-

ns

6,7,

11~13

Data-in Hold Time to DQS-In

(DQ & DM)

tDH

0.5

-

0.5

-

0.5

-

0.6

-

ns

DQ & DM Input Pulse Width

tDIPW

1.75

-

1.75

-

1.75

-

2

-

ns

Read DQS Preamble Time

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

CK

Read DQS Postamble Time

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

CK

Write DQS Preamble Setup Time

tWPRES

0-

0

-

0

-

0

-

CK

Write DQS Preamble Hold Time

tWPREH

0.25

-

0.25

-

0.25

-

0.25

-

CK

Write DQS Postamble Time

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

CK

Mode Register Set Delay

tMRD

2-

2

-

2

-

2

-

CK

Exit Self Refresh to Any Execute

Command

tXSC

200

-

200

-

200

-

200

-

CK

8

Average Periodic Refresh Interval

tREFI

-

15.6

-

15.6

-

15.6

-

15.6

us

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