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For price, delivery, and to place orders, please contact Hittite Microwave Corporation:

12 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373

Visit us at www.hittite.com, or Email at sales@hittite.com

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HMC268LM1 General Biasing & Application Circuit

50 W

25 W

RF IN

(PIN 8)

Vds2

Vds1

Vdd (Pin 2)

C2

C1

C1

C2 C1

C2

V 1

(Pin 7)

gg

V 2

(Pin 6)

gg

RF OUT

(PIN 4)

Optimal biasing of the HMC268LM1 SMT two stage low noise amplifier Vdd, Vgg1 & Vgg2 DC ports is described below.

The LNA schematic is repeated below. Note the recommended addition of the external bypass chip capacitors. For

additional general MMIC amplifier biasing guidance, please refer to the Hittite Microwave “MMIC Amplifier Biasing Pro-

cedure” found on page 8-8 or on www.hittite.com under the Application Note section.

A) Do not exceed 3.5 Vdc on internal circuit nodes Vds1 and Vds2 (internal Drain to Source

voltages). Calculate the Vds1 & 2 voltages from the LNA schematic above.

B) Do not bias Vdd, Vgg1 & Vgg2 DC ports in such a way that Vgs becomes a positive voltage

(internal Gate to Source voltage).

The biasing may be adjusted slightly to achieve either low noise with lowest DC power consumption or low noise with

highest output power. Be sure to adhere to the IMPORTANT DC LIMITS above while optimizing performance.

A) Low Noise and Low Power Consumption: Vdd = 3.5 Vdc @ ldd = 30 mA. Set Vgg1 = Vgg2.

B) Low Noise and High Output Power: Vdd = 4.0 Vdc @ ldd = 45 mA. Utilizing Vgg1 & Vgg2 nominal bias

is obtained for a typical ldd current of 30 mA for the second or “output” stage and 15 mA for the first

stage. The first step to bias the amplifier is to tune the Vgg1 = -1.0 Vdc and Vgg2 to drive 30 mA for the

full amplifier. Then Vgg1 is reduced to obtain ldd = 45 mA of current for the amplifier.

HMC268LM1 Biasing Schemes for Performance Trade-Offs

HMC268LM1

SMT MMIC LOW NOISE

AMPLIFIER, 20 - 32 GHz

v03.1201