64Mx72 bits

Unbuffered DDR SO-DIMM with PLL

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/Apr. 02

1

HYMD264M726A(L)8-J/M/K/H/L

DESCRIPTION

Hynix HYMD264M726A(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline

Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix

HYMD264M726A(L)8-J/M/K/H/L series consists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a

200pin glass-epoxy substrate.

Hynix HYMD264M726A(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control

inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on

both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high

bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable

latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD264M726A(L)8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function

is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-

tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Pactor

HYMD264M726A(L)8-J

166MHz (*DDR333)

SSTL_2

200pin Unbuffered SO-DIMM

HYMD264M726A(L)8-M

133MHz (*DDR266:2-2-2)

HYMD264M726A(L)8-K

133MHz (*DDR266A)

HYMD264M726A(L)8-H

133MHz (*DDR266B)

HYMD264M726A(L)8-L

100MHz (*DDR200)

•

512MB (64M x 72) Unbuffered DDR SO-DIMM based

on 32Mx8 DDR SDRAM

•

JEDEC Standard 200-pin small outline dual in-line

memory module (SO-DIMM)

•

2.5V +/- 0.2V VDD and VDDQ Power supply

•

All inputs and outputs are compatible with SSTL_2

interface

•

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz/166MHz

•

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

•

Data inputs on DQS centers when write (centered

DQ)

•

Data strobes synchronized with output data for read

and input data for write

•

Programmable /CAS Latency 2 / 2.5 supported

•

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

tRAS Lock-out function supported

•

Internal four bank operations with single pulsed

/RAS

•

Auto refresh and self refresh supported

•

8192 refresh cycles / 64ms

•

2.00” (50.80mm) Height PCB with Double sided

components

* JEDEC Defined Specifications compliant