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HYMD264G726C4M-L Datasheet(PDF) 8 Page - Hynix Semiconductor |
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HYMD264G726C4M-L Datasheet(HTML) 8 Page - Hynix Semiconductor |
8 / 16 page HYMD264G726C(L)4M-M/K/H/L Rev. 0.1 / Mar. 2003 8 DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition Speed Unit Note -M -K -H -L Operating Current IDD0 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 2540 2360 2360 2270 mA Operating Current IDD1 One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 3350 2990 2990 2810 mA Precharge Power Down Standby Current IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min) 1010 mA Idle Standby Current IDD2F /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM 1550 1370 1370 1280 mA Active Power Down Standby Current IDD3P One bank active; Power down mode; CKE=Low, tCK=tCK(min) 1100 mA Idle Quiet Standby Current IDD2Q /CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS and DM TBD mA Active Standby Current IDD3N /CS=HIGH; CKE=HIGH; One bank; Active- Precharge; tRC=tRAS(max); tCK=tCK(max); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 1730 1550 1550 1550 mA Operating Current IDD4R Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA 5690 4970 4970 3890 mA Operating Current IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM, and DQS inputs changing twice per clock cycle 5690 4970 4970 3890 Auto Refresh Current IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 4490 4130 4130 3860 Self Refresh Current IDD6 CKE=<0.2V; External clock on; tCK=tCK(min) Normal 404 mA Low Power 377 mA Operating Current - Four Bank Operation IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition 6140 5960 5960 5960 mA Random Read Current IDD7A 4banks active read with activate every 20ns, AP(Auto Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS inputs changing twice per clock cycle; 100% addresses changing once per clock cycle TBD mA |
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