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HYMD216M646CL6-D43 Datasheet(PDF) 10 Page - Hynix Semiconductor |
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HYMD216M646CL6-D43 Datasheet(HTML) 10 Page - Hynix Semiconductor |
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10 / 19 page  HYMD216M646C(L)6-D43/D4/J Rev. 0.1 / Apr. 2003 10 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol DDR333 Unit Note Min Max Row Cycle Time tRC 60 - ns Auto Refresh Row Cycle Time tRFC 72 - ns Row Active Time tRAS 42 70K ns Active to Read with Auto Precharge Delay tRAP 18 - ns 16 Row Address to Column Address Delay tRCD 18 - ns Row Active to Row Active Delay tRRD 12 - ns Column Address to Column Address Delay tCCD 1- CK Row Precharge Time tRP 18 - ns Write Recovery Time tWR 15 - ns Last Data-In to Read Command tDRL 1- CK Auto Precharge Write Recovery + Precharge Time tDAL (tWR/tCK) + (tRP/tCK) -CK 15 System Clock Cycle Time CL = 2.5 tCK 612 ns CL = 2 7.5 12 ns Clock High Level Width tCH 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.7 0.7 ns DQS-Out edge to Clock edge Skew tDQSCK -0.6 0.6 ns DQS-Out edge to Data-Out edge Skew tDQSQ -0.45 ns Data-Out hold time from DQS tQH tHP -tQHS -ns 1, 10 Clock Half Period tHP min (tCL,tCH) -ns 1,9 Data Hold Skew Factor tQHS -0.55 ns 10 Valid Data Output Window tDV tQH-tDQSQ ns Data-out high-impedance window from CK, /CK tHZ -0.7 0.7 ns 17 Data-out low-impedance window from CK, /CK tLZ -0.7 0.7 ns 17 Input Setup Time (fast slew rate) tIS 0.75 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.75 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 0.8 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 0.8 - ns 2,4,5,6 |
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