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HYMD212G726BLS4M-L Datasheet(PDF) 9 Page - Hynix Semiconductor |
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HYMD212G726BLS4M-L Datasheet(HTML) 9 Page - Hynix Semiconductor |
9 / 17 page HYMD212G726B(L)S4M-M/K/H/L Rev. 0.1 / Dec. 2003 9 DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS=0V) Parameter Symbol Test Condition Speed Unit Note -M -K -H -L Operating Current IDD0 One bank; Active - Precharge; tRC=tRC(min); tCK= tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 3530 3290 3290 3050 mA Operating Current IDD1 One bank; Active - Read - Precharge; Burst Length =2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 3530 3290 3290 3050 mA Precharge Power Down Standby Current IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min) 970 mA Idle Standby Current IDD2F /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS, and DM 2250 2090 2090 1930 mA Active Power Down Standby Current IDD3P One bank active; Power down mode; CKE=Low, tCK=tCK(min) 1130 mA Active Standby Current IDD3N /CS=HIGH, CKE=HIGH; One bank; Active- Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 2570 2410 2410 2250 mA Operating Current IDD4R Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA 4330 3930 3930 3690 mA Operating Current IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM, and DQS inputs changing twice per clock cycle 6770 5870 5870 4790 Auto Refresh Current IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 4190 3950 3950 3710 Self Refresh Current IDD6 CKE=<0.2V; External clock on; tCK =tCK(min) Normal 446 mA Low Power 398 mA Operating Current - Four Bank Operation IDD7 Four bank interleaving with BL=4 Refer to the following page for detailed test condition 5630 5390 5390 5150 mA |
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