Rev.

1.1

/

May.

2005

10

11

200pin Unbuffered DDR SDRAM SO-DIMMs

256MB, 32M x 64 Unbuffered SO-DIMM: HYMD232M646D[L][P]6

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol

Test Condition

Speed

Unit

Note

DDR400B DDR333 DDR266A DDR266B

IDD0

One bank; Active - Precharge; tRC=tRC(min);

tCK=tCK(min); DQ,DM and DQS inputs changing

twice per clock cycle; address and control inputs

changing once per clock cycle

600

520

440

440

mA

IDD1

One bank; Active - Read - Precharge; Burst

Length=2; tRC=tRC(min); tCK=tCK(min); address

and control inputs changing once per clock cycle

640

600

520

520

mA

IDD2P

All banks idle; Power down mode; CKE=Low,

tCK=tCK(min)

80

80

80

80

mA

IDD2F

/CS=High, All banks idle; tCK=tCK(min); CKE=

High; address and control inputs changing once

per clock cycle. VIN=VREF for DQ, DQS and DM

480

400

320

320

mA

IDD3P

One bank active; Power down mode; CKE=Low,

tCK=tCK(min)

120

120

120

120

mA

IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-Pre-

charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM

and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once

per clock cycle

440

380

320

320

mA

IDD4R

Burst=2; Reads; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK=tCK(min); IOUT=0mA

1040

960

840

840

mA

IDD4W

Burst=2; Writes; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK=tCK(min); DQ, DM and DQS

inputs changing twice per clock cycle

1040

960

840

840

mA

IDD5

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz; dis-

tributed refresh

840

800

720

720

mA

IDD6

CKE=<0.2V; External clock on; tCK

=tCK(min)

Normal

24

24

24

24

mA

Low Power

12

12

12

12

mA

IDD7

Four bank interleaving with BL=4 Refer to the fol-

lowing page for detailed test condition

1240

116010401040

mA