 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HYMP512R72CP8-C4 Datasheet(PDF) 9 Page - Hynix Semiconductor |
|
||||||||||||||||||||||||||||||
HYMP512R72CP8-C4 Datasheet(HTML) 9 Page - Hynix Semiconductor |
|
|
9 / 26 page  Rev. 0.2 / Sep. 2008 9 1 240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx72): HYMP525R72CP4 / HYMP512P72CP4 IO0 I/O1 I/O2 I/O3 /RS0 VSS /RS1 DQ0 DQ1 DQ2 DQ3 DQS0 /DQS0 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS DQ8 DQ9 DQ10 DQ11 DQS1 /DQS1 DQ16 DQ17 DQ18 DQ19 DQS2 /DQS2 DQ24 DQ25 DQ26 DQ27 DQS3 /DQS3 DQ48 DQ49 DQ50 DQ51 DQS6 /DQS6 DQS DQ56 DQ57 DQ58 DQ59 DQS7 /DQS7 /RS0 /RS1 DQ32 DQ33 DQ34 DQ35 DQS4 /DQS4 DQ40 DQ41 DQ42 DQ43 DQS5 /DQS5 CB0 CB1 CB2 CB3 DQS8 /DQS8 DQ4 DQ5 DQ6 DQ7 DQS9 /DQS9 DQ12 DQ13 DQ14 DQ15 DQS10 /DQS10 DQ20 DQ21 DQ22 DQ23 DQS11 /DQS11 DQ28 DQ29 DQ30 DQ31 DQS12 /DQS12 DQ52 DQ53 DQ54 DQ55 DQS15 /DQS15 DQ60 DQ61 DQ62 DQ63 DQS9 /DQS9 DQ36 DQ37 DQ38 DQ39 DQS13 /DQS13 DQ44 DQ45 DQ46 DQ47 DQS14 /DQS14 CB4 CB5 CB6 CB7 DQS17 /DQS17 ODT0 CKE0 /PCK7** /WE 1:2 R E G I S T E R PCK7** /RESET** /CAS /RAS BA0-BA1*** A0-A13*** /S1* /RST /S0* RODT1 = > ODT1: SDRAMs D18-D35 ODT1 CKE1 RODT0 = > ODT0: SDRAMs D0-D17 RCKE1 = > CKE1: SDRAMs D18-D35 RCKE0 = > CKE0: SDRAMs D0-D17 /RA0-RA12 = > A0 -A12 : SDRAMs D0-D35 /RWE = > /WE: SDRAMs D0-D35 /RCAS = > /CAS: SDRAMs D0-D35 /RRAS = > /RAS: SDRAMs D0-D35 /RBA0-RBA1 = > BA0 -BA1 : SDRAMs D0-D35 /RS1 to /CS : SDRAMs D18-D35 /RS0 to /CS : SDRAMs D0-D17 Notes: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 22 Ohms +/- 5%. 3. /RS0 and /RS1 altemate between the bottom and surface sides of the DIMM. * /S0 connects to D/CS0 and /S1 connects to CSR on a pair of Registers. /S1 connects to D/CS and /S0 connects to /CSR on another pair of Registers. ** /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers. *** A13-15, BA2 have the optional pull down resistors(100K ohms), which is not indicated here. SA0 SA1 SA2 W P SCL SDA A0 A1 A2 Serial PD SCL U0 SDA VDD SPD VREF VDD/VDDQ VSS Serial PD DO to D35 DO to D35 DO to D35 P L L OE CK0 /CK0 /RESET PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMs D0-D35 /PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMs D0-D35 PCK7 = > CK: Register /PCK7 = > /CK: Register IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS D0 D18 D1 D19 D2 D20 D3 D21 D8 D26 D4 D22 D5 D23 D6 D24 D7 D25 IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS IO0 I/O1 I/O2 I/O3 DQS /CS DM I/O0 I/O1 I/O2 I/O3 /DQS DQS /CS DM / DQS D9 D27 D10 D28 D11 D29 D12 D30 D17 D35 D13 D31 D14 D32 D15 D33 D16 D34 Register C0 A1 C1 PAR_IN PPO /QERR VSS VDD Register C0 A1 C1 PAR_IN PPO /QERR VDD Register C0 A1 C1 PAR_IN PPO /QERR VSS VDD Register C0 A1 C1 PAR_IN PPO /QERR VDD VDD VDD Signals for Address and Command Parity Function Register A1 and A2 and A2 share the a part of Addr/Cmd input signal set. Register B1 and B2 share the rest part of Addr/Cmd input signal set. The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: “Register Options for Unused Address inputs” /Err_Out |
Similar Part No. - HYMP512R72CP8-C4 |
|
Similar Description - HYMP512R72CP8-C4 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
